The present invention relates to a computer program product, method, and system for hardware model conversion.
In recent LSI development, upsizing of LSI circuits is proceeding. The mainstream technique for that purpose is to design a new circuit by using the past circuit designing resources in order to shorten the design period. As a technique for enhancing operation frequency, there is a know method of pipelining the existing circuit designing resources described in JP-A-8-44773. Particularly, in a disk array system equipped with a plurality of disk drives having a RAID (Redundant Arrays of Independent/Inexpensive Disks) configuration, an error correcting circuit with a large number of logic stages is required. Accordingly, pipelining the error correcting circuit is effective in improving performance. Although an HDL (Hardware Description Language) has been the mainstream design language used for LSI design, as the upsizing of LSI circuits proceeds, the HDL is being replaced by a system level description language (such as SpecC or SystemC) that is more abstract than the HDL. JP-A-2004-21841 discloses a technique for inputting an RTL (register transfer level) Verilog HDL source and converting it to a program that can be executed by a computer.